Exemplary embodiments of the present invention relate to a non-volatile memory device, and more particularly, to a three-dimensional non-volatile memory device and a method for fabricating the same.
In a memory string structure with a U shape of a non-volatile memory device such as a three-dimensional flash memory, a source selection gate and a drain selection gate are formed on a memory string. Such a memory string structure is desirable in terms of device characteristics as compared with a vertical string structure in which selection gates are formed on and under a memory string. In order to operate such a U shaped memory string, a transistor for electrically coupling the selection gates to a bottom is used. The transistor is called a pipe channel transistor.
Two strings coupled to each other through a source and a drain are electrically coupled to each other through the pipe channel transistor. In order to electrically couple the two strings to each other, the pipe channel transistor is needed to be turned on.
FIG. 1 is a cross-sectional view illustrating a conventional three-dimensional non-volatile memory device.
Referring to FIG. 1, a pipe gate 12 is formed on a bottom substrate 11. The bottom substrate 11 has a structure in which a semiconductor substrate and an insulation layer are stacked. The pipe gate 12 is etched to form a pipe channel hole 12A.
A memory string is formed on the pipe gate 12. The memory string includes a first string MS1 and a second string MS2. The first string MS1 and the second string MS2 include a plurality of memory cells, respectively. The first string MS1 is coupled to the second string MS2 through a pipe channel 17B. The first string MS1 and the second string MS2 include first insulation layers 13 and control gate electrodes 14. The first insulation layer 13 and the control gate electrode 14 are alternately stacked for multiple times. The memory string includes a pair of cell channel holes 15 which are coupled to each other through the pipe channel hole 12A. A substantially U-shaped string structure is formed by the cell channel holes 15 and the pipe channel hole 12A, the plurality of memory cells of the first string MS1 are serially coupled to one another, and the plurality of memory cells of the second string MS2 are serially coupled to one another. A memory layer 16, cell channels 17A and a second insulation layer 19 fill the cell channel holes 15. The memory layer 16, a pipe channel 17B and the second insulation layer 19 fill the pipe channel hole 12A. The memory layer 16 is formed by stacking a blocking layer, a charge trap layer and a tunnel insulation layer. The control gate electrodes 14 of each string are separated from each other by a slit 18 and a third insulation layer 20 fills the slit 18.
In FIG. 1, a pipe channel transistor (PC Tr) is formed below the memory string by the pipe gate 12 and the pipe channel 17B. In order to form the pipe gate 12, processes of depositing a polysilicon layer and forming a trench and a sacrificial layer (silicon nitride layer), and a chemical mechanical polishing (CMP) process, and the like may be performed. In the CMP process, a silicon nitride layer CMP process of using a polysilicon layer as a stop layer or a polysilicon CMP process of using a silicon nitride layer as a stop layer may be performed. However, since these CMP processes are difficult to ensure uniformity and reproduction, it may be difficult to apply the CMP processes to mass production.
Furthermore, since it is difficult to use a metal gate as the pipe gate 12 of the pipe channel transistor, an N+ doped polysilicon is used for the pipe gate 12. Use of the metal gate is avoided since a subsequent cell formation process is difficult to perform.
The pipe gate 12 is turned on at the time of a program or read operation. However, when the pipe gate 12 is turned on, the control gate electrodes 14 of the memory string are simultaneously turned on. In such a case, since the resistance of the N+ doped polysilicon is relatively large, speed reduction due to resistive capacitance delay (RC delay) occurs.